Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses

ABSTRACT

In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices from one of N master processors via a system bus controller and K slave buses. The K slave buses are configured to couple to the P slave devices. The system bus controller dynamically maps address spaces of the P slave devices. The slave bus decoder enables the one of the P slave devices to connect to one of the K slave buses when the one of the P slave devices is addressed by the one of the N master processors. The slave bus decoder is controlled by the system bus controller. In another embodiment of the present invention, the system bus controller includes an arbiter, a mapping circuit, and a switching circuit. The arbiter arbitrates access requests from N master processors via N master buses and generates arbitration signals. The mapping circuit stores mapping information to dynamically map an address space of K slave devices coupled to K slave buses based on the arbitration signals. The switching circuit connects the N master buses to K slave buses based on the arbitration signals and the mapping information.

BACKGROUND

[0001] 1. Field of the Invention

[0002] This invention relates to computer architecture. In particular,the invention relates to multiprocessor systems.

[0003] 2. Description of Related Art

[0004] In a multiprocessor system, several processors are connected to abus to communicate with each other and with other devices. A processorthat has control of the bus is referred to as a master. Examples of amaster include central processing unit (CPU), digital signal processor(DSP), and direct memory access (DMA) controller. A device that can onlyrespond to a bus operation (e.g., read, write) initiated by a master isreferred to as a slave. Examples of a slave include memory device,serial input/output device, and universal asynchronous receiver andtransceiver (UART).

[0005] In a typical multiprocessor system, there are several masters andslaves. The masters usually have to compete for the use of the bus. Whena master is using the bus, other masters have to wait. The problem iseven more severe when several masters want to access several slaves atthe same time.

[0006] Therefore, there is a need to have a technique to utilize the busefficiently.

SUMMARY

[0007] The present invention is a method and apparatus to provideefficient access to multiple slave devices via a plurality of slavebuses. In one embodiment of the present invention, a slave interfacecircuit is coupled between one of P slave devices and K slave buses. Theslave interface circuit includes a slave access circuit and a slave busdecoder. The slave access circuit provides access to the one of P slavedevices from one of N master processors via a system bus controller andK slave buses. The K slave buses are configured to couple to the P slavedevices. The system bus controller dynamically maps address spaces ofthe P slave devices. The slave bus decoder enables the one of the Pslave devices to connect to one of the K slave buses when the one of theP slave devices is addressed by the one of the N master processors. Theslave bus decoder is controlled by the system bus controller. In anotherembodiment of the present invention, the system bus controller includesan arbiter, a mapping circuit, and a switching circuit. The arbiterarbitrates access requests from N master processors via N master busesand generates arbitration signals. The mapping circuit stores mappinginformation to dynamically map an address space of P slave devicescoupled to K slave buses based on the arbitration signals. The switchingcircuit connects the N master buses to K slave buses based on thearbitration signals and the mapping information.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The features and advantages of the present invention will becomeapparent from the following detailed description of the presentinvention in which:

[0009]FIG. 1 is a diagram illustrating a system in which one embodimentof the invention can be practiced.

[0010]FIG. 2 is a diagram illustrating a slave interfacing circuit shownin FIG. 1 according to one embodiment of the invention.

[0011]FIG. 3 is a diagram illustrating a system bus controller shown inFIG. 1 according to one embodiment of the invention.

[0012]FIG. 4 is a diagram illustrating a memory map for the slavedevices according to one embodiment of the invention.

[0013]FIG. 5A is a diagram illustrating an example of a system accordingto one embodiment of the invention.

[0014]FIG. 5B is a diagram illustrating a memory map for the systemshown in FIG. 5A according to one embodiment of the invention.

[0015]FIG. 5C is a diagram illustrating a truth table for the slaveaccess decoder for the memory map shown in FIG. 5B according to oneembodiment of the invention.

DESCRIPTION

[0016] The present invention is a technique to provide efficient accessto slave devices by multiple master processors. Accessing the slavedevices is carried out via a number of slave buses. A system buscontroller is interfaced between the master processor buses and theslave buses to allow any one of the master processors to access to anyone of the slave buses. Each of the slave devices is connected to allthe slave buses via an interface circuit. The system bus controller hasa mapping circuit to dynamically map the address space of the slavedevices according to mapping information. The mapping information isupdated by a supervisor processor.

[0017] In the following description, for purposes of explanation,numerous details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be apparent toone skilled in the art that these specific details are not required inorder to practice the present invention. In other instances, well-knownelectrical structures and circuits are shown in block diagram form inorder not to obscure the present invention.

[0018]FIG. 1 is a diagram illustrating a system 100 in which oneembodiment of the invention can be practiced. The system 100 includes Nmaster processors 110 ₁ to 110 _(N), N master buses 115 ₁ to 115 _(N), asystem bus controller 120, K slave buses 125 ₁ to 125 _(K), P slaveinterface circuits 130 ₁ to 130 _(P), and P slave devices 140 ₁ to 140_(P).

[0019] Each of the N processors 110 ₁ to 110 _(N) is coupled to each ofthe N master buses 115 ₁ to 115 _(N), respectively. The masterprocessors 110 ₁ to 110 _(N) are any processors that are capable ofcontrolling their corresponding buses master buses 115 ₁ to 115 _(N).The ability to control the bus includes asserting mastership, issuingaccess control signals (e.g., read and write), issuing address and data,etc. A processor that can have control of a bus is referred to as amaster. A device that can only receive information on the bus isreferred to as a slave. Examples of the processors 110 ₁ to 110 _(N)include microprocessor, digital signal processor, micro-controller,direct memory access (DMA) controller, etc. Examples of a slave includememory devices, peripheral devices (e.g., serial communication, parallelinput/output devices). The N master buses 115 ₁ to 115 _(N) may behomogeneous or heterogeneous depending on the type of the correspondingN processors 110 ₁ to 110 _(N). Examples of include the PeripheralInterconnect Component (PCI) bus, the Industry Standard Adapter (ISA),or any specially designed bus.

[0020] The system bus controller 120 is interfaced between the N masterbuses 115 ₁ to 115 _(N) and the K slave buses 125 ₁ to 125 _(K). Thesystem bus controller 120 controls the access to the P slave devices 140₁ to 140 _(P) from the N master processors 110 ₁ to 110 _(N) bydynamically mapping the address spaces of the P slave devices 140 ₁ to140 _(P) according to the system access requests. Through the system buscontroller 120, any one of the N processors 110 ₁ to 110 _(N) can accessto any one of the P slave devices 140 ₁ to 140 _(P). The system buscontroller 120 arbitrates all the access requests from the to resolveany access conflicts. The arbitration may be based on some predefined,or static, priority, variable, or dynamic, priority, or a combination ofboth static and dynamic priorities. The system bus controller 120 alsoswitches the appropriate connections to connect the N master buses 115 ₁to 115 _(N) to the K slave buses 125 ₁ to 125 _(K) dynamically accordingto current system demands and access requests. In addition, the systembus controller 120 generates control signals to the P slave interfacecircuits 130 ₁ to 130 _(P) to enable the connection of the correspondingslave devices to the K slave buses 125 ₁ to 125 _(K).

[0021] The K slave buses 125 ₁ to 125 _(K) provide access to the P slavedevices 140 ₁ to 140 _(P). The K slave buses 125 ₁ to 125 _(K) may behomogenous or heterogeneous, and are compatible to all the P slavedevices 140 ₁ to 140 _(P). The P slave interface circuits 130 ₁ to 130_(P) are circuits that provide interface between each of the P slavedevices 140 ₁ to 140 _(P) to the K slave buses 125 ₁ to 125 _(K).

[0022]FIG. 2 is a diagram illustrating a slave interfacing circuit 130 jshown in FIG. 1 according to one embodiment of the invention. The slaveinterfacing circuit 130 j includes a slave access circuit 210, a slavebus decoder 220, and a gating circuit 230.

[0023] The slave access circuit 210 is connected to the slave device 140j and the K slave buses 125 ₁ to 125 _(K) to provide access to the slavedevice 140 j from one of the N master processors 110 ₁ to 110 _(N) viathe system bus controller 120. The slave access circuit includes K busbuffers 212 ₁ to 212 _(K) which are connected to the K slave buses 125 ₁to 125 _(K), respectively. Each of the K bus buffers 212 ₁ to 212 _(K)is enabled by the slave bus decoder 220. In one embodiment, theenablement of the K bus buffers 212 ₁ to 212 _(K) is mutually exclusivesuch that at any time at most one of the K bus buffers 212 ₁ to 212 _(K)is enabled. In other words, at any time, the slave device 140 j isconnected to at most one of the K slave buses 125 ₁ to 125 _(K). Sinceany one of the K bus buffers 212 ₁ to 212 _(K) can be enabled by theslave bus decoder 220 under the control of the bus controller 120, theslave device 140 j can be connected to any one of the K slave buses 125₁ to 125 _(K).

[0024] The slave bus decoder 220 is coupled to the slave access circuit210 to enable the slave device 140 j to connect to one of the K slavebuses 125 ₁ to 125 _(K) when the slave device 140 j is addressed by oneof the N master processors 110 ₁ to 110 _(N) The slave bus decoder 220is controlled by the system bus controller 120. The slave bus decoder220 may be implemented as a S-to-2^(S) decoder having S inputs D₀, D₁, .. . , D_(S), and an enable input E. When E is asserted active, e.g.,LOW, the slave bus decoder 220 generates an active output correspondingto the S inputs. When E is de-asserted inactive, e.g., HIGH, the slavebus decoder 220 is disabled and generates all inactive outputs (e.g.,HIGH) which disables all the bus buffers 212 ₁ to 212 _(K). The S and Einputs are provided by the bus controller 120 (FIG. 1). Note that analternative embodiment is to combine the slave bus decoder 220 with thegating circuit 230 in a composite decoding circuit.

[0025] The gating circuit 230 receives the control signals provided bythe bus controller 120. The control signals include N group of signals.Each group of signals corresponds to a master processor. The gatingcircuit 230 may be implemented as a multiplexer that route the controlsignals of the master processor that has control of the slave device toa slave bus so that its decoder inputs can be selected. This can befurther explained in the example shown in FIGS. 5A through 5C.

[0026]FIG. 3 is a diagram illustrating the system bus controller 120shown in FIG. 1 according to one embodiment of the invention. The systembus controller 120 includes an arbiter 310, a mapping circuit 320, aswitching circuit 330, and a slave access decoder 340.

[0027] The arbiter 310 arbitrates the access requests from the N masterprocessors via the N master buses. The arbiter 310 generates arbitrationsignals as result of the arbitration. The arbitration signals indicatewhich master processor is given access to the slave device if there isaccess conflict. The corresponding master processors are informed of thearbitration so that it can proceed with the access if the access isgranted, or attempt to access again if the access is denied.

[0028] The mapping circuit 320 store mapping information 322 todynamically map the address space of the K slave devices according tosystem requirements and access requests. The mapping information 322 isupdated by a supervisor processor in the system. This supervisorprocessor may be an external processor or one of the N master processors110 ₁ to 110 _(N). In the illustrative example shown in FIG. 3, themaster processor 110 ₁ is designated as the supervisor processor. Themapping information 322 may be stored in a memory which occupies at adesignated location. This memory may be a random access memory (RAM), aflash memory, or any read/write memory. Other master processors can alsoaccess the memory information 322 SO that access data can be obtained.The mapping circuit 320 generate control signals to the switchingcircuit 330 and the slave access decoder 340. The mapping circuit 320may also pass the relevant master bus signals to the slave addressdecoder 340.

[0029] The switching circuit 330 is coupled to the arbiter 310 and themapping circuit 320 to connect the N master 115 ₁ to 115 _(N) to the Kslave buses 125 ₁ to 125 _(K) based on the arbitration signals and themapping information. The switching circuit 330 includes N master ports332 ₁ to 332 _(N) and K slave ports 3361 to 336K. Each of the master andslave ports may be a buffer device or a multiplexer that can be enabledto connect to corresponding bus. The switching circuit 330 NK data pathsto connect any of the N master ports to the any of the K slave ports. Adecoding logic circuit is used to assure that path conflict is avoided.

[0030] The slave access decoder 340 decodes the addresses issued by theN master processors 110 ₁ to 110 _(N), either directly or via themapping circuit 320. The slave access decoder 340 generates controlsignals to the P slave interface circuits 130 ₁ to 130 _(P) For eachslave interface circuit, there is a set of control signals to ensurethat at any time, at most one slave device is allowed to connected toone of the K slave buses 125 ₁ to 125 _(K).

[0031]FIG. 4 is a diagram illustrating a memory map for the slavedevices according to one embodiment of the invention.

[0032] The address map shows the possible mapping of the slave devicesto occupy the address space of each of the master processors 110 ₁ to110 _(N). The memory space is divided into L address blocks. Eachaddress block provides memory spaces for the P slave devices 140 ₁ to140 _(P). The address field of each of the slave device is divided intothree fields: A, B, and C. Field A is provided by the mappinginformation 322 as determined by the supervisor processor. Field B isprovided by the slave address decoder 340 (FIG. 3) to select individualslave device within each address block.

[0033]FIG. 5A is a diagram illustrating an example of a system 500according to one embodiment of the invention. For simplicity andclarity, only the relevant elements are shown. The system 500 includesthree master processors 510 ₁ to 510 ₃, a bus controller 520, 4 slavebuses 525 ₁ to 525 ₄, and 8 slave devices 540 ₁ to 540 ₈. For clarity,the slave interface circuits are not shown.

[0034] In this example, suppose it is decided that slave devices 1, 2,4, and 5 are assigned to slave bus 1; slave devices 3, 6, and 8 areassigned to slave bus 2; and slave device 7 is assigned to slave bus 4.In this example, slave bus 3 is not used. Suppose that afterarbitration, master processor 1 has control of the slave bus 1, masterprocessor 2 has control of slave bus 2, and master processor 3 hascontrol of slave bus 4. From s slave device's point of view, it does notknow which master processor is in control of the slave bus that it isconnected to. The bus controller 520 performs the connecting of themaster buses to the appropriate slave buses via the slave ports. Inaddition, the supervisor processor, say the master processor 510 ₁updates the mapping information in the mapping circuit to reflect thisassignment and memory mapping.

[0035]FIG. 5B is a diagram illustrating a memory map for the systemshown in FIG. 5A according to one embodiment of the invention.

[0036] Suppose that each slave device occupies an address range of 64K.Then, field A is used to allocate the 8 slave devices to the 4 slavebuses by assigning the 8 slave devices in a slave block. Therefore,field A has at least 2 bits. Field B is used to allocate each of the 8slave devices to the corresponding slave block. Therefore, field B hasat least 3 bits. Field C is used to allocate the address range of 64Kfor each slave device. Therefore, filed C has 16 bits. The entire memoryspace has a minimum size of 64K×4×8=2M address range. If more than 2Maddress space is used, there will be gaps or unused memory sub-spaces.

[0037] The memory space is divided into 4 memory blocks 550 ₁ to 550 ₄corresponding to slave buses 1 to 4 525 ₁ to 525 ₄, respectively. Slaveblock 550 ₁ occupies the memory address range from 00 000 xx . . . xx to00 111 xx . . . xx (in binary), where x indicates don't cares and is16-bit. Similarly, slave blocks 5502 to 5504 occupy memory addressranges from 01 000 xx . . . xx to 01 111 xx . . . xx, from 10 000 xx . .. xx to 10 111 xx . . . xx, and from 11 000 xx . . . xx to 11 111 xx . .. xx, respectively. The cross-hatched memory range indicates the memoryaddress range occupied by the slave device as assigned.

[0038]FIG. 5C is a diagram illustrating a truth table for the slaveaccess decoder for the memory map shown in FIG. 5B according to oneembodiment of the invention.

[0039] In this example, the slave access decoder 340 (FIG. 3) may beimplemented as a set of three look-up tables, each look-up tablecorresponding to each master. The look-up table may be implemented by arandom access memory, or an re-configurable programmable logic circuit.The address to the look-up table is the upper address bits of the memoryspace shown in FIG. 5B, i.e., fields A and B. The outputs of the look-uptable are the control signals connected to all 8 slave bus decoder 220 ₁to 220 ₈ as shown as the element 220 in FIG. 2. In addition, at eachslave device there is a gating circuit to gate the control signalsaccording to which master is in control of which slave bus.

[0040] Since each slave bus decoder has 2 decode inputs and one enableinput, for eight slave devices, there are 8×3=24 control signals. Thesecontrol signals form into eight group, each group goes to each slavedevice and consists of three bits D₁ D₀ E where D₁ D₀ are the decoderinputs and E is the enable input to the 2-to-4 slave bus decoder 220.When the E input of a slave bus decoder is de-asserted HIGH, thecorresponding slave device is disconnected from all the slave busesbecause all the bus buffers are disabled, or become high impedance. Inthis case, the D₁ D₀ inputs become don't care.

[0041] The contents of the look-up tables shown in FIG. 5C are anabstract representation of all three look-up tables, where x indicatesdon't cares. There are twenty-four bits total divided into eight groupsof three bits. Each group goes to each slave device. If a masterprocessor generates an address that does not correspond to the slavedevice that can be connected to the slave bus under its control, therewill be an error. For example, if master 1 generates an address 11 001xx . . . xx, there will be an error.

[0042] While this invention has been described with reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications of the illustrativeembodiments, as well as other embodiments of the invention, which areapparent to persons skilled in the art to which the invention pertainsare deemed to lie within the spirit and scope of the invention.

What is claimed is:
 1. An apparatus comprising: a slave access circuitcoupled to one of P slave devices and K slave buses to provide access tothe one of the P slave devices from one of N master processors via asystem bus controller, the K slave buses being configured to couple tothe P slave devices, the system bus controller dynamically mappingaddress spaces of the P slave devices; and a slave bus decoder coupledto the slave access circuit to enable the one of the P slave devices toconnect to one of the K slave buses when the one of the P slave devicesis addressed by the one of the N master processors, the slave busdecoder being controlled by the system bus controller.
 2. The apparatusof claim 1 wherein the slave access circuit comprises: K bus bufferscoupled to the K slave buses to buffer bus signals corresponding toaccess signals to the one of the P slave devices, the K bus buffersbeing enabled by the slave bus decoder.
 3. The apparatus of claim 2wherein each of the K bus buffers is connected to each of the K slavebuses.
 4. An apparatus comprising: an arbiter to arbitrate accessrequests from N master processors via N master buses, the arbitergenerating arbitration signals; a mapping circuit to store mappinginformation to dynamically map an address space of P slave devicescoupled to K slave buses based on the arbitration signals; and aswitching circuit coupled to the arbiter and the mapping circuit toconnect the N master buses to K slave buses based on the arbitrationsignals and the mapping information.
 5. The apparatus of claim 4 furthercomprising: a slave access decoder coupled to the arbiter and the Nmaster processors to decode addresses issued by the N master processors,the slave access decoder generating control signals to P slave interfacecircuits, each of the P slave interface circuits being connected to eachof the P slave devices.
 6. The apparatus of claim 5 wherein the mappinginformation is provided by a supervisor processor.
 7. The apparatus ofclaim 4 wherein the mapping information is accessible to the N masterprocessors.
 8. A method comprising: providing access to one of the Pslave devices from one of N master processors via a system buscontroller and K slave buses, the K slave buses being configured tocouple to the P slave devices; dynamically mapping address spaces of theP slave devices by the bus controller; enabling the one of the P slavedevices to connect to one of the K slave buses by a slave bus decoderwhen the one of the P slave devices is addressed by the one of the Nmaster processors; and controlling the slave bus decoder by the systembus controller.
 9. The method of claim 8 wherein providing accesscomprises: buffering bus signals corresponding to access signals to theone of the P slave devices by K bus buffers; and enabling the K busbuffers by the slave bus decoder.
 10. The method of claim 9 whereinbuffering the bus signals comprises: connecting each of the K busbuffers to each of the K slave buses.
 11. An method comprising:arbitrating access requests from N master processors via N master busesby an arbiter, the arbiter generating arbitration signals; storingmapping information in a mapping circuit to dynamically map an addressspace of P slave devices coupled to K slave buses based on thearbitration signals; and connecting the N master buses to K slave busesbased on the arbitration signals and the mapping information.
 12. Themethod of claim 11 further comprising: decoding addresses issued by theN master processors by a slave access decoder; generating controlsignals to P slave interface circuits by the slave access decoder, eachof the P slave interface circuits being connected to each of the P slavedevices.
 13. The method of claim 12 wherein the mapping information isprovided by a supervisor processor.
 14. The method of claim 11 whereinthe mapping information is accessible to the N master processors.
 15. Asystem comprising: a bus controller coupled to N bus masters and K slavebuses; P slave devices; and P slave interface circuits coupled to the Pslave devices and the K slave buses, each of the P slave interfacecircuits comprising: a slave access circuit coupled to one of the Pslave devices and the K slave buses to provide access to the one of theP slave devices from one of the N master processors via the system buscontroller, the K slave buses being configured to couple to the P slavedevices, the system bus controller dynamically mapping address spaces ofthe P slave devices, and a slave bus decoder coupled to the slave accesscircuit to enable the one of the P slave devices to connect to one ofthe K slave buses when the one of the P slave devices is addressed bythe one of the N master processors, the slave bus decoder beingcontrolled by the system bus controller.
 16. The system of claim 15wherein the slave access circuit comprises: K bus buffers coupled to theK slave buses to buffer bus signals corresponding to access signals tothe one of the P slave devices, the K bus buffers being enabled by theslave bus decoder.
 17. The system of claim 16 wherein each of the K busbuffers is connected to each of the K slave buses.
 18. A systemcomprising: N bus masters having N master buses; P slave devices coupledto K slave buses; and A system bus controller coupled to the N busmasters and the K slave buses, the bus controller comprising: an arbiterto arbitrate access requests from the N master processors via the Nmaster buses, the arbiter generating arbitration signals, a mappingcircuit to store mapping information to dynamically map an address spaceof P slave devices coupled to K slave buses based on the arbitrationsignals, and a switching circuit coupled to the arbiter and the mappingcircuit to connect the N master buses to K slave buses based on thearbitration signals and the mapping information.
 19. The system of claim18 wherein the system bus controller further comprising: a slave accessdecoder coupled to the arbiter and the N master processors to decodeaddresses issued by the N master processors, the slave access decodergenerating control signals to P slave interface circuits, each of the Pslave interface circuits being connected to each of the P slave devices.20. The system of claim 19 wherein the mapping information is providedby a supervisor processor.
 21. The system of claim 18 wherein themapping information is accessible to the N master processors.